1. general description the 74avc8t245-q100 is an 8-bit, dual supply transceiver that enables bidirectional level translation. it features two 8-bit input-output ports (an and bn), a direction control input (dir), an output enable input (oe ) and dual supply pins (v cc(a) and v cc(b) ). both v cc(a) and v cc(b) can be supplied at any voltage between 0.8 v and 3.6 v making the device suitable for translating between any of the low voltage nodes (0.8 v, 1.2 v, 1.5 v, 1.8 v, 2.5 v and 3.3 v). pins an, oe and dir are referenced to v cc(a) and pins bn are referenced to v cc(b) . a high on dir allows transmission from an to bn and a low on dir allows transmission from bn to an. the output enable input (oe ) can be used to disable the outputs so the buses are effectively isolated. the device is fully specified for pa rtial power-down applications using i off . the i off circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. in suspend mode when either v cc(a) or v cc(b) are at gnd level, both an and bn are in the high-impedance off-state. this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? wide supply voltage range: ? v cc(a) : 0.8 v to 3.6 v ? v cc(b) : 0.8 v to 3.6 v ? complies with jedec standards: ? jesd8-12 (0.8 v to 1.3 v) ? jesd8-11 (0.9 v to 1.65 v) ? jesd8-7 (1.2 v to 1.95 v) ? jesd8-5 (1.8 v to 2.7 v) ? jesd8-b (2.7 v to 3.6 v) ? esd protection: ? mil-std-883, method 3015 class 3b exceeds 8000 v ? hbm jesd22-a114e class 3b exceeds 8000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) ? maximum data rates: ? 380 mbit/s ( ? 1.8 v to 3.3 v translation) 74avc8t245-q100 8-bit dual supply translating tr ansceiver with configurable voltage translation; 3-state rev. 2 ? 6 september 2013 product data sheet
74avc8t245_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 september 2013 2 of 24 nxp semiconductors 74avc8t245-q100 8-bit dual supply translating transceiver; 3-state ? 260 mbit/s ( ? 1.1 v to 3.3 v translation) ? 260 mbit/s ( ? 1.1 v to 2.5 v translation) ? 210 mbit/s ( ? 1.1 v to 1.8 v translation) ? 150 mbit/s ( ? 1.1 v to 1.5 v translation) ? 100 mbit/s ( ? 1.1 v to 1.2 v translation) ? suspend mode ? latch-up performance exceeds 100 ma per jesd 78 class ii ? inputs accept voltages up to 3.6 v ? i off circuitry provides partial power-down mode operation ? multiple package options 3. ordering information 4. functional diagram table 1. ordering information type number package temperature range name description version 74avc8t245pw-q100 ? 40 ? c to +125 ? c tssop24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm sot355-1 74AVC8T245BQ-Q100 ? 40 ? c to +125 ? c dhvqfn24 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 ? 5.5 ? 0.85 mm sot815-1 fig 1. logic symbol 001aai472 oe dir v cc(a) v cc(b) 22 2 3 a1 a2 a3 a4 a5 a6 a7 a8 b1 b2 b3 b4 b5 b6 b7 b8 4567891 0 21 20 19 18 17 16 15 14
74avc8t245_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 6 september 2013 3 of 24 nxp semiconductors 74avc8t245-q100 8-bit dual supply translating transceiver; 3-state 5. pinning information 5.1 pinning fig 2. logic diagram (one channel) 001aai473 to other seven channels dir a1 v cc(a) v cc(b) oe b1 (1) this is not a supply pin. the substrate is attached to this pad using conductive die atta ch material. there is no electrical or mechanical requi rement to solder this pad. however, if it is soldered, the solder land should remain floating or be connected to gnd. fig 3. pin configuration tssop24 fig 4. pin configuration dhvqfn24 9 & |